Our Architecture team has expertise to understand requirements and come up with Design specifications. Our team of architects can help on performance analysis for a system as well as with details of micro-architecture for RTL implementation.
Our experienced engineers are capable to start from a high level specification and take the design through the complete ASIC implementation process. They posses experience in cross-functional interaction with Verification team, Physical Design team, PTE team and SW team. They can capture complex design intent in synthesizable Verilog or VHDL code as well as experiences in integrating 3rd party cores. Using industry standard tools our engineers can do detailed analysis of the design including syntactic correctness, power consumption, testability, constraints definition, clock synchronization and routability.
Creating the best balance of performance, power, and area intent from a given RTL has become an increasingly complex task. Our designers run industry standard tools to convert RTL to gate level netlist, ready to be taken into design implementation phase. The synthesis is for specific target technology and timing constraints include details such as clocks, input/output timings, loading, false, multi-cycle paths.
Our team is experienced in enabling early and concurrent design-for-test (DFT) planning, testability, analysis, and verification. Appropriate ATPG patterns can achieve downstream correlation for greater predictability, the highest quality netlist, and fewer iterations for physical and test design flows.
Verification team spans the levels of understanding required for complex SoC verification from TLM (Transaction Level Modeling) through RTL, gates, and transistors. They have experience of multiple verification methodologies including Assertion Based Verification (ABV), the Open Verification Methodology (OVM) and the Universal Verification Methodology (UVM) to increase testbench productivity, automation and reusability. Our engineers come up with test plan by understanding design specs and write test cases to cover functionality as well as to provide code coverage analysis.
ARM based SoC verification and Power Aware simulations are the strong areas where team has built their expertise over a period of time.
Gate level simulations further check quality of synthesized netlist. Performing gate-level simulation gives us the opportunity to check that our complex designs still works properly after being Synthesized and Placed and Routed. Additionally, we use the gate-level simulations to obtain switching activies for each gate in the design. This allows us to estimate power and energy.
Design teams must ensure their RTL functions according to specification, while also coping with the complex transformations that their RTL undergoes along the path to silicon. Equivalence checking employs formal methods to exhaustively verify that a transformed netlist is functionally equivalent to the “golden” RTL or netlist. Cadence® equivalence checking technology works completely independent of implementation algorithms, eliminating false positives and catching logic bugs that would otherwise make it into the implemented chip.
Our Designers have expertise in test vector development for wafer and packaged part testing, targeted for digital and analog blocks. Our engineers have expertise in achieving test time reduction by applying innovative techniques during test vector development phase on digital blocks and analog as well. Our team is experienced in thoroughly debugging the test vectors during wafer testing and packaged part testing on Automatic Test Equipment (ATE).
Our engineers perform physical partitioning considering block sizes, pinouts and special placement requirements to enable successful completion of the chip while meeting area, performance and power targets. At this stage, block constraints are generated, time budgets defined and power, clock distribution is planned.
Design engineers perform automated placement driven by timing constraints, clock tree synthesis, power, signal and special net routing. Our engineers are trained in variety of industry standard advanced EDA tools.
STA includes Setup, hold and I/O timing checks with the help of timing constraints, derived from Synthesis stage. All timing paths in design are thoroughly checked to ensure that timing is met in various timing corners. STA is performed on hierarchical and flat netlist, both.
DRC, LVS, ERC and Antenna checks are performed in this phase and density, slotting and special rules are checked. After data base is thoroughly checked, designers then prepare GDSII database release to the foundry for “The tapeout”.
We offer mask design services for standard cells libraries, gate arrays libraries and digital, analog IP components. We also have expertise in memory, high speed IO mask design and full custom blocks.
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