Design Verification
Req ID:
US/12-1/DV
Experience: 7+
years
Location: San
Diego
Qualification:
B.Tech
Job
Description:
The candidate will perform test
planning, developing test bench in System Verilog / UVM
methodology, writing either C or System Verilog tests, perform
coverage analysis and closure, and run and debug regressions in one
of these areas:
- Chip level testing with C tests running on ARM processors and
integrating subsystems, cores, and peripherals.
- Bus integration and subsystem level testing using System
Verilog/UVM environment.
- Block level verification of clocks.
- Power verification.
- Security verification.
- Performance verification.
- Audio codec.
- Apply formal verification.
- Gate simulation and vector generation
Requirement:
Strong RTL debug skills and test
planning skills are required. Either System Verilog/UVM test bench
development (Vera is also acceptable) or C test development
experience is required. Coverage analysis and closure experience is
highly preferred.
Domains: SOC
verification (chip DV is acceptable), ARM processor, AMBA bus (AXI,
AHB), DDR, peripheral and core integration (DMA, crypto engine,
power management module, USB, MIPI SLIMBus, etc.)
The ideal candidate would have wireless SOC DV experience and is
proficient at test planning, RTL debug, writing C test to run on an
ARM processor, developing System Verilog/UVM testbench, working
with AMBA bus protocols, code and functional coverage
closure.
Design Verification
Req ID:
US/12-2/DV
Experience: 5+
years
Location: San
Diego
Qualification:
B.Tech
Job
Description:
The candidate will perform test
planning, developing test bench in System Verilog / UVM
methodology, writing either C or System Verilog tests, perform
coverage analysis and closure, and run and debug regressions in one
of these areas:
- Chip level testing with C tests running on ARM processors and
integrating subsystems, cores, and peripherals.
- Bus integration and subsystem level testing using System
Verilog/UVM environment.
- Block level verification of clocks.
- Power verification.
- Security verification.
- Performance verification.
- Audio codec.
- Apply formal verification.
- Gate simulation and vector generation
Requirement:
Strong RTL debug skills and test
planning skills are required. Either System Verilog/UVM test bench
development (Vera is also acceptable) or C test development
experience is required. Coverage analysis and closure experience is
highly preferred.
Domains: SOC
verification (chip DV is acceptable), ARM processor, AMBA bus (AXI,
AHB), DDR, peripheral and core integration (DMA, crypto engine,
power management module, USB, MIPI SLIMBus, etc.)
The ideal candidate would have wireless SOC DV experience and is
proficient at test planning, RTL debug, writing C test to run on an
ARM processor, developing System Verilog/UVM testbench, working
with AMBA bus protocols, code and functional coverage
closure.
Physical Design
Req ID:
US/13-1/PD
Experience: 10+
years
Location: San
Diego
Qualification:
B.Tech
Job
Description:
- Work on backend design of various connectivity and wireless
chips
- Floorplanning / place and route, power grid and clock tree
design and analysis
- Static Timing Analysis and signal integrity closure,
extraction, DRC and LVS
- Use semi-custom layout where appropriate to maximize density
performance and power efficiency
- Implement DFM and DFT requirements
- Respond quickly to engineering changes
Requirement:
- Able to deal with Chip Top level
complexity from Placement, CTS, Routing and timing
closure
- Proficient in timing
closure, constraints, SI prevention/fixing, Clk synthesis, power
planning
- Expert in Synopsys ICC, Magma
Talus, Mentor Olympus, Cadence FE tool set.
- Experience in Mentor caliber
tools to run Physical verification
- Knowledge of I/R drop analysis is
a Pulse
- Excellent interpersonal and
analytical skills with the ability to work
independently.
- Highly motivated, excellent team
spirit, product and customer oriented.
- Experience in Tcl/Tk, PERL
is a Plus
Physical Design
Req ID:
US/13-2/PD
Experience: 4+
years
Location: San
Diego
Qualification:
B.Tech
Job
Description:
- Work on backend design of various
connectivity and wireless chips
- Floorplanning / place and route,
power grid and clock tree design and analysis
- Static Timing Analysis and signal
integrity closure, extraction, DRC and LVS
- Use semi-custom layout where
appropriate to maximize density performance and power
efficiency
- Implement DFM and DFT
requirements
- Respond quickly to engineering
changes
Requirement:
- Must be able to take the
Hardmacro through P&R from Netlist to GDS including timing
closure and Physical verification.
- Experience in Design
Automation
- Understanding timing closure,
constraints, SI prevention/fixing, power planning, CTS.
- Proficient in Synopsys ICC, Magma
Talus or Cadence FE tool set.
- Experience in Mentor caliber
tools to run Physical verification
- Knowledge of I/R drop analysis is
a Plus
- Proficient in UNIX, Tcl/Tk and/or
PERL is required
- Excellent interpersonal and
analytical skills with the ability to work
independently.
- Highly motivated, excellent team
spirit, product and customer oriented.
RTL Design
Req ID:
US/11-2/RTL
Experience: 5+
years
Location: San
Diego
Qualification:
B.Tech
Job
Description:
The candidate will perform Block
level as well as Full Chip Synthesis. Constraints needs to be
generated as sub-system level and later migrate it to Top-level.
He/She should be able to perform linting and review the same.
Formal Verification bench need to setup at Top-level. Static Timing
Analysis reports should be able to review and provide design
changes to designers to achieve proper timing within the
chip.
Requirement:
- Detailed knowledge of ASIC design
including architecture, verification of integrated systems, RTL
design, synthesis, and timing closure
- Minimum of 4 years of digital
ASIC design experience including Verilog coding, linting,
synthesis, formal verification (LEC), and Static Timing
Analysis.
- Specific experience with
Spyglass, Zero-in, Conformal LEC, Conformal LP, Synopsys DC/PT,
PTSI is required
- Experience with VLSI designs
targeting 45nm or below preferred
- Experience with low-power
high-volume products is desired
